A fundamental design challenge in creating a memory cell of an electrically erasable programmable read only memory (EEPROM) device is to use a controllable and reproducible electrical effect that has sufficient non-linearity so that the memory cell (1) can be written to (or erased) at one voltage in less than one millisecond (1 ms) and can be read at another voltage, and (2) the data within the memory cell must remain unchanged for more than ten (10) years.
Prior art stacked/split gate EEPROM technology requires (1) special multi-polysilicon materials, (2) different gate oxide thicknesses, and (3) modified doping profiles. These prior art requirements create process complexity and high cost when embedded into a complementary metal oxide semiconductor (CMOS) process.
FIG. 1 illustrates a schematic diagram of a prior art memory cell 100 of an electrically erasable programmable read only memory (EEPROM) device. Memory cell 100 comprises one P-channel metal oxide semiconductor (PMOS) transistor 110 and one P-channel metal oxide semiconductor (PMOS) capacitor 120. The PMOS capacitor 120 is formed by connecting together the source, drain and substrate of a PMOS transistor.
The PMOS transistor 110 may be referred to as PMOS program transistor 110. The PMOS capacitor 120 may be referred to as PMOS control capacitor 120. The gate of the PMOS program transistor 110 and the gate of the PMOS control capacitor 120 are connected together (i.e., shorted together) and are isolated from the other active elements. The shorted gates of the PMOS program transistor 110 and the PMOS control capacitor 120 are collectively referred to as a “floating gate” 130. Charges (in amounts that represent either a zero (“0”) representation or a one (“1”) representation) may be written to the floating gate 130. In order to avoid well bias interference, the PMOS program transistor 110 and the PMOS control capacitor 120 are each located in a separate N well.
The prior art memory cell 100 is written to by injecting drain avalanche hot electrons into the floating gate 130. For PMOS operation (as shown in FIG. 1) low voltage is applied to the control gate and drain of PMOS control capacitor 120 and high voltage is applied to the source/well of PMOS program transistor 110. The channel of PMOS program transistor 110 is turned on and hot electrons are generated at the high electric field region at the drain junction (designated “VINJ” in FIG. 1). With positive voltage on the control gate of PMOS control transistor 120, some hot electrons with high energy will pass through the silicon-silicon dioxide (Si—SiO2) potential barrier and be injected into the floating gate 130.
The prior art memory cell 100 is erased by applying a high voltage to the control gate of the PMOS control transistor 120 and to the ground drain and source of the PMOS program transistor 110. Electrons on the floating gate 130 will pass through the gate oxide between the floating gate 130 and the control gate of the PMOS control capacitor 120 by Fowler-Nordheim (FN) tunneling process and go to the substrate. A description of the physics of the Fowler-Nordheim (FN) tunneling process is set forth in U.S. Pat. No. 5,225,362.
During programming, most control gate voltage should be coupled between the floating gate 130 and the drain/source of the PMOS program transistor 110 to facilitate electron injection to the floating gate 130 but not further to the control gate of the PMOS control transistor 120. This requires the capacitance between the floating gate 130 and the control gate to be large. On the other hand, during the erase procedure, more control gate voltage should be coupled between the floating gate 130 and the control gate, so that electrons can tunnel from the floating gate 130 to the substrate by the Fowler-Nordheim (FN) tunneling process. This requires the capacitance between the floating gate 130 and the control gate to be small.
These two contradictory requirements for the control gate capacitance during the program procedure and the erase procedure leave a narrower operation window. This results in poor data retention and slower speeds for an EEPROM that comprises one PMOS program transistor and one PMOS control capacitor.
To improve the operational speed and data retention for an EEPROM device, EEPROM designers have sometimes placed an additional capacitor in the basic memory cell. This approach has one large capacitor for the programming operation and one small capacitor for the erase operation. Capacitor coupling techniques are used to achieve a favorable electric field for both the programming operation and the erase operation.
The floating gate of an added capacitor has to be filled with hot electrons. Hot electrons that pass through gate oxide will create oxide damage. Oxide damage degrades the endurance of a memory cell. Endurance is measured by how many program/erase cycles the gate oxide can tolerate before unacceptable damage occurs. Therefore, one major drawback to adding an extra capacitor is that it degrades EEPROM memory cell endurance performance.
Another drawback to adding an extra capacitor is that it significantly increases the size of the basic memory cell. This significantly lowers the EEPROM array density. Additional chip area is required for the extra capacitors. This increases the cost.
Another drawback of prior art CMOS EEPROM technology is the speed of the programming procedure. The programming procedure is carried out by utilizing drain avalanche hot electrons. Because the efficiency of generating and injecting the drain avalanche hot electrons is low, programming times are relatively long. The programming time is usually one hundred milliseconds (100 ms) or longer. Even the improved coupling provided by using additional capacitors only reduces the programming time to about twenty milliseconds (20 ms).
FIG. 2 illustrates a schematic diagram of a prior art memory cell 200 of an erasable programmable read only memory (EEPROM) device that comprises a control capacitor and an erase capacitor. Memory cell 200 comprises program transistor 210, control capacitor 220, floating gate 230, erase capacitor 240 and read transistor 250 coupled together as shown in FIG. 2.
Prior art memory cell 200 operates in the same manner as that described for prior art memory cell 100. That is, the gate of the PMOS program transistor 210 and the gate of the PMOS control capacitor 220 are connected together (i.e., shorted together) and are isolated from the other active elements. The shorted gates of the PMOS program transistor 210 and the PMOS control capacitor 220 are collectively referred to as a “floating gate” 230. Charges (in amounts that represent either a “zero” (“0”) representation or a “one” (“1”) representation) may be written to the floating gate 230.
Prior art memory cell 200 comprises a PMOS erase capacitor 240 to facilitate the erase operation. The gate of the PMOS erase capacitor 240 is also connected to the floating gate 230. Prior art memory cell 200 also comprises a PMOS read transistor 250 to facilitate the read operation. The gate of the PMOS read transistor 250 is also connected to the floating gate 230. The PMOS read transistor 250 has nothing to do with the program/erase operations of memory cell 200.
The programming operation is carried out by Drain Avalanche Hot Carrier (DAHC) electron injection. Electrons from the edge of the drain junction of the program transistor 210 are injected into the floating gate 230. The erase operation is carried out by Fowler-Nordheim (FN) tunneling. Electrons from the floating gate 230 tunnel to the substrate of the erase capacitor 240.
FIG. 3 illustrates an illustrative memory cell layout design 300 for memory cell 200. The program transistor 210 and the erase capacitor 240 and the read transistor 250 are the same size. The program transistor 210 has an area ratio of one to twenty seven (1:27) with respect to the area of the control capacitor 220. During the operation of memory cell 200 this relatively high value for the coupling ratio helps lower the value of the erase voltage and the value of the program voltage.
However, the relatively high value for the coupling ratio leads to excess oxide damage. This is because (1) the large control capacitor 220 has to be filled up from a small hot electron injection point, and (2) during the erase process all the electrons stored on the large control capacitor 220 must be removed from a small erase point. This is one of the major reasons that complementary metal oxide semiconductor (CMOS) non-volatile memory (NVM) memory cells usually are capable of only one thousand (1,000) or so program/erase cycles.
In order to lower the operating voltage, particularly the Fowler-Nordheim (FN) tunneling voltage that is commonly used in erase operations, the coupling ratio between the control capacitor 220 and the erase capacitor 240 must be high. The coupling ratio is usually more than ten to one (10:1). In the example shown in FIG. 3, the coupling ratio between the control capacitor 220 and the erase capacitor 240 is twenty-seven to one (27:1). That is, the area of the control capacitor 220 is twenty seven (27) times the area of the erase capacitor 240.
Adding in the effect of the area of the floating gate 230 can increase the coupling ratio to as much as fifty to one (50:1). During the erase procedure the electrons that are stored in the area of the control capacitor 220 and in the area of the floating gate 230 will need to discharge through a much smaller erase area in the erase capacitor 240. This means that many electrons will need to pass through the gate oxide of the erase capacitor 240.
In mainstream stacked gate flash memory the control ratio is usually about one and two tenths to one (1.2:1). This is a fundamental reason that stacked gate flash memory can have an endurance of up to one hundred thousand (100,000) program/erase cycles. As previously mentioned, the endurance of CMOS compatible non-volatile memory (NVM) memory cells is usually only about one thousand (1,000) program/erase cycles.
Therefore, there is a need in the art for a system and method for enhancing the erase performance of a CMOS compatible non-volatile memory (NVM) memory cell of an EEPROM device. In particular, there is a need in the art for a system and method that is capable of simultaneously decreasing the erase voltage and decreasing the coupling ratio (while maintaining the erase speed) in a CMOS compatible non-volatile memory (NVM) memory cell of an EEPROM device.
The present invention provides a CMOS compatible EEPROM memory cell that comprises three CMOS N type (NMOS) transistors. The first NMOS transistor serves as a control capacitor, the second NMOS transistor serves as an erase capacitor, and the third NMOS transistor serves as a program capacitor. The gates of the three NMOS transistors are connected together to form a floating gate.
The size of the control capacitor is selected to provide a coupling ratio between the control capacitor and the erase capacitor that has a value of approximately two to one. Each NMOS transistor of the CMOS compatible EEPROM memory cell is isolated from an underlying P substrate by a Deep N Well isolation structure. This allows the well bias voltage to be isolated from other active elements on the semiconductor wafer.
Bias voltages are applied to the P well of the control capacitor and to the P well of the erase capacitor. The EEPROM memory cell of the present invention is erased with a Fowler-Nordheim (FN) tunneling current that is obtained by using a lower amplitude of erase voltage and a lower coupling ratio compared to prior art methods. This results in a significant improvement in the endurance of the EEPROM memory cell as measured by the number of program/erase cycles that the EEPROM memory cell can perform.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.